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dc.contributor.authorSun, J
dc.contributor.authorLiu, Y
dc.contributor.authorDong, JS
dc.contributor.authorShi, L
dc.contributor.authorAndré, E
dc.date.accessioned2017-10-23T04:28:54Z
dc.date.available2017-10-23T04:28:54Z
dc.date.issued2013
dc.identifier.issn1049-331X
dc.identifier.doi10.1145/2430536.2430537
dc.identifier.urihttp://hdl.handle.net/10072/172870
dc.description.abstractModeling and verifying complex real-time systems are challenging research problems. The de facto approach is based on Timed Automata, which are finite state automata equipped with clock variables. Timed Automata are deficient in modeling hierarchical complex systems. In this work, we propose a language called Stateful Timed CSP and an automated approach for verifying Stateful Timed CSP models. Stateful Timed CSP is based on Timed CSP and is capable of specifying hierarchical real-time systems. Through dynamic zone abstraction, finite-state zone graphs can be generated automatically from Stateful Timed CSP models, which are subject to model checking. Like Timed Automata, Stateful Timed CSP models suffer from Zeno runs, that is, system runs that take infinitely many steps within finite time. Unlike Timed Automata, model checking with non-Zenoness in Stateful Timed CSP can be achieved based on the zone graphs. We extend the PAT model checker to support system modeling and verification using Stateful Timed CSP and show its usability/scalability via verification of real-world systems.
dc.description.peerreviewedYes
dc.languageEnglish
dc.language.isoeng
dc.publisherACM Special Interest Group
dc.relation.ispartofpagefrom3-1
dc.relation.ispartofpageto3-29
dc.relation.ispartofissue1
dc.relation.ispartofjournalACM Transactions on Software Engineering and Methodology
dc.relation.ispartofvolume22
dc.subject.fieldofresearchComputer Software not elsewhere classified
dc.subject.fieldofresearchComputer Software
dc.subject.fieldofresearchInformation Systems
dc.subject.fieldofresearchcode080399
dc.subject.fieldofresearchcode0803
dc.subject.fieldofresearchcode0806
dc.titleModeling and verifying hierarchical real-time systems using stateful timed CSP
dc.typeJournal article
dc.type.descriptionC1 - Articles
dc.type.codeC - Journal Articles
gro.hasfulltextNo Full Text
gro.griffith.authorDong, Jin-Song


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