FPGA implementation of wavelet coherence for EEG and ERP signals
Embargoed until: 2019-06-01
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This paper presents the design and implementation of wavelet coherence (WC) processor on low cost field-programmable gate array (FPGA). This design is adapted to estimate the wavelet coherence between two EEG signals in a minimal delay in order to support real time applications. The produced CWT coefficients were saved in static RAM chips and prepared for the WC analysis starting with the smoothing operation as an essential computation for the WC algorithm. The WC algorithm was analyzed in the means of choosing the suitable word length for the stages of the design and to simplify the employed functions in the algorithm. Several controllers that handle signal transmission among the design components were designed using hardware description language (VHDL). By using 4 parallel-processing smoothing circuits, the design is capable to calculate the coherogram between two EEG signals (1024 point each) in a total time of 128.64 ms. Image quality methods were applied for coherogram comparison between hardware and software. Hardware results were compared against the rigorous software standard WC according to the following measures; normalized mean square error (NMSE), normalized average difference (NAD) and structural content (SC) are 0.0045, 0.0485 and 0.921 respectively.
Microprocessors and Microsystems
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Electrical and Electronic Engineering not elsewhere classified