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dc.contributor.advisorHarrison, Barry
dc.contributor.authorTanner, Philip
dc.date.accessioned2019-03-28T05:06:55Z
dc.date.available2019-03-28T05:06:55Z
dc.date.issued1996
dc.identifier.doi10.25904/1912/3110
dc.identifier.urihttp://hdl.handle.net/10072/365212
dc.description.abstractAs each successive generation of MOS devices is scaled down to meet the requirements for increased speed and integration, the demands placed on dielectric layers and semiconductor-dielectric interfaces become more severe. Improved process cleanliness and novel growth techniques have come a long way in producing uniform, low-leakage thermal oxides on silicon with the required thicknesses of 5nm and less. This study focuses on the all-important interface region between silicon and SiO2 and in particular a class of charge trap located there known as the slow trap. These traps, variously called border traps or switching oxide states, exchange charge with the silicon substrate on time scales from milliseconds to hours depending on their energy level and separation from the interface. The chemical nature of slow traps, fast interface traps and fixed oxide charge is discussed in a review of current literature which also considers a range of measurement techniques used for their electrical characterisation. The creation of these defects during the initial oxide growth, as a result of subsequent processing, or during normal device operation is also reviewed, with particular attention being given to the process of plasma etching. It is well known that during this important fabrication step, damage to MOS structures can occur due to charge build-up on isolated gate materials and direct exposure to hgh energy plasma emissions. A number of techniques are commonly used to electrically characterise charge traps at the interface and in the bulk of the oxide. However, they are inadequate when measuring the wide range of response times of slow traps. Consequently, a new technique has been developed as part of this study which simultaneously measures slow trap densities and their response times over a range of gate voltages of a MOS capacitor. The new technique, called Slow Trap Profiling, is described in detail with examples given which highlight its advantages over other methods, particularly the quasi-static capacitance-voltage technique. Slow trap profiling is then successfully used to measure slow traps created by constant current or voltage stressing of wet etched MOS capacitors in the first instance, and by RF plasma etching of the gate electrode in the second. Both these processes can degrade the performance of MOS devices by creating defects at and near the oxide-silicon interface. A necessary part of the plasma etch study was the accurate measurement of the endpoint of the polysilicon gate etching process. To satisfy this requirement, an endpoint detection system based on the principles of ellipsometry was developed and fitted to an etch reactor, enabling overetch times to be measured with an accuracy of less than 1s. Details of the system design and performance are given. Slow trap profiles obtained from oxides of varying thickness and growth conditions reveal a range of trap energy levels throughout the silicon bandgap and beyond, with response times ranging fkom 20ms to many seconds. The capture and emission rates were found to be quite different and the reasons for this are discussed. Comparisons of slow trap characteristics between plasma etching and electrical stress support the results of others that indicate similar damage mechanisms affecting the interface region during both processes. After creating the initial damage, changes in slow trapping with room temperature and higher temperature anneals are also measured and discussed. The original contribution of this thesis is summarised in the following points - + A new technique has been developed and successfully used to measure a wide range of slow trap characteristics in MOS capacitors; namely density, gate voltage or energy location, and response times or charge trapping and emission rates. + An accurate endpoint detection system has been developed and used in the plasma etching of polysilicon gate material. Endpoint accuracy of less than 1s was achieved and at least 80% photoresist coverage could be tolerated. + The plasma etch study has revealed the extent of damage to different MOS structures during the critical overetch period. In all cases, slow traps are generated and their presence can be easily overlooked when using more common measurement technques. + The theory that plasma etching and electrical stress exhibit similar damage mechanisms is supported by the study of slow trap creation in both cases. The aim of this study has been to highlight the importance of slow traps in the field of MOS technology and to demonstrate the advantages of a new measurement techmque which can be used for their characterisation. With the scaling of future MOS devices, the quality of the oxide-silicon interface where slow traps are found becomes more critical. It is proposed that the new slow trap profiling technique will be a useful tool in the monitoring of slow trap densities and trapping rates as a function of oxide growth conditions and subsequent device processing. In our laboratory, it has already proved useful in other studies of ultrathin nitrided oxides growth on silicon and silicon carbide, a wide bandgap material.
dc.languageEnglish
dc.publisherGriffith University
dc.publisher.placeBrisbane
dc.rights.copyrightThe author owns the copyright in this thesis, unless stated otherwise.
dc.subject.keywordsSlow traps
dc.subject.keywordsMOS
dc.subject.keywordsSlow Trap Profiling
dc.subject.keywordsMetal oxide semiconductors
dc.subject.keywordsSilicon oxide
dc.titleSlow Traps in MOS Structures: a Study of High Field and Plasma Induced Trapping in the Si-SiO2 Interface Region
dc.typeGriffith thesis
gro.facultyScience, Environment, Engineering and Technology
gro.rights.copyrightThe author owns the copyright in this thesis, unless stated otherwise.
gro.hasfulltextFull Text
dc.contributor.otheradvisorDimitrijev, Sirna
dc.contributor.otheradvisorYeow, Tong
gro.identifier.gurtIDgu1335141365973
gro.identifier.ADTnumberadt-QGU20051201.093533
gro.thesis.degreelevelThesis (PhD Doctorate)
gro.thesis.degreeprogramDoctor of Philosophy (PhD)
gro.departmentSchool of Microelectronic Engineering
gro.griffith.authorTanner, Philip G.


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