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dc.contributor.authorHóu, Z
dc.contributor.authorSanan, D
dc.contributor.authorTiu, A
dc.contributor.authorLiu, Y
dc.contributor.authorHoa, KC
dc.contributor.authorDong, JS
dc.date.accessioned2020-08-25T00:44:47Z
dc.date.available2020-08-25T00:44:47Z
dc.date.issued2020
dc.identifier.issn0168-7433
dc.identifier.doi10.1007/s10817-020-09579-4
dc.identifier.urihttp://hdl.handle.net/10072/396682
dc.description.abstractThe SPARC instruction set architecture (ISA) has been used in various processors in workstations, embedded systems, and in mission-critical industries such as aviation and space engineering. Hence, it is important to provide formal frameworks that facilitate the verification of hardware and software that run on or interface with these processors. In this work, we give the first formal model for multi-core SPARC ISA and Total Store Ordering (TSO) memory model in Isabelle/HOL. We present two levels of modelling for the ISA: The low-level ISA model, which is executable, covers many features specific to SPARC processors, such as delayed-write for control registers, windowed general registers, and more complex memory access. We have tested our model extensively against a LEON3 simulation board, the test covers both single-step executions and sequential execution of programs. We also prove some important properties for our formal model, including a non-interference property for the LEON3 processor. The high-level ISA model is an abstraction of the low-level model and it provides an interface for memory operations in multi-core processors. On top of the high-level ISA model, we formalise two TSO memory models: one is an adaptation of the axiomatic SPARC TSO model (Sindhu et al. in Formal specification of memory models, Springer, Boston, 1992; SPARC in The SPARC architecture manual version 8, 1992. http://gaisler.com/doc/sparcv8.pdf), the other is a new operational TSO model which is suitable for verifying execution results. We prove that the operational model is sound and complete with respect to the axiomatic model. Finally, we give verification examples with two case studies drawn from the SPARCv9 manual.
dc.description.peerreviewedYes
dc.languageEnglish
dc.language.isoeng
dc.publisherSpringer Science and Business Media LLC
dc.relation.ispartofjournalJournal of Automated Reasoning
dc.subject.fieldofresearchFormal methods for software
dc.subject.fieldofresearchSoftware testing, verification and validation
dc.subject.fieldofresearchArtificial intelligence
dc.subject.fieldofresearchSoftware engineering
dc.subject.fieldofresearchTheory of computation
dc.subject.fieldofresearchcode461203
dc.subject.fieldofresearchcode461208
dc.subject.fieldofresearchcode4602
dc.subject.fieldofresearchcode4612
dc.subject.fieldofresearchcode4613
dc.titleAn Isabelle/HOL Formalisation of the SPARC Instruction Set Architecture and the TSO Memory Model
dc.typeJournal article
dc.type.descriptionC1 - Articles
dcterms.bibliographicCitationHóu, Z; Sanan, D; Tiu, A; Liu, Y; Hoa, KC; Dong, JS, An Isabelle/HOL Formalisation of the SPARC Instruction Set Architecture and the TSO Memory Model, Journal of Automated Reasoning, 2020
dc.date.updated2020-08-23T23:40:48Z
dc.description.versionAccepted Manuscript (AM)
gro.description.notepublicThis publication has been entered as an advanced online version in Griffith Research Online.
gro.rights.copyright© 2020 Springer Netherlands. This is an electronic version of an article published in Journal of Automated Reasoning, 2020. Journal of Automated Reasoning is available online at: http://link.springer.com/ with the open URL of your article.
gro.hasfulltextFull Text
gro.griffith.authorHou, Zhe
gro.griffith.authorDong, Jin-Song


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