Hardware implementations of an image compressor for mobile communications
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Mobile communications has seen an explosive growth in the past five years with the integration of communications devices and multimedia applications. Transport connections set up over wireless links are frequently plagued by such problems as a high bit error rate (BER), frequent disconnections of the mobile users, and low wireless bandwidth that may change dynamically. Proposed developments in B3G and 4G wireless services will further challenge researchers to come up with efficient devices that can handle the huge data transmission. Fast and low-power compression algorithms are greatly needed to accommodate the specification. This paper highlights and analyzes various next-generation image-compression algorithms developed on the basis of image transmission via a wireless channel. In addition, the performance comparisons between the proposed hardware implementations are shown. Two important findings are discovered: First, the high-speed reconfigurable devices called FPSoC are the best hardware implementation. Second, a vector-quantizationbased VSPIHT algorithm offers the best solution of parallel processing in efficient hardware architecture. This article serves as a reference point for researchers developing image-compression algorithms for next-generation mobile-communications devices.
Journal of Communications Technology and Electronics
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Electrical and Electronic Engineering not elsewhere classified