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dc.contributor.authorI Reaz, M.en_US
dc.contributor.authorAmin, Nowshaden_US
dc.contributor.authorIbrahimy, M.en_US
dc.contributor.authorMohd-Yasin, F.en_US
dc.contributor.authorMohammad, A.en_US
dc.contributor.editorN/Aen_US
dc.date.accessioned2017-05-03T11:49:40Z
dc.date.available2017-05-03T11:49:40Z
dc.date.issued2008en_US
dc.date.modified2012-09-04T22:55:42Z
dc.identifier.doi10.1109/CCECE.2008.4564488en_US
dc.identifier.urihttp://hdl.handle.net/10072/40072
dc.description.abstractA zero skew clock routing methodology has been developed to help design team speed up their clock tree generation process. The methodology works by breaking up the clock net into smaller partitions, then inserting clock buffers to drive each portion, and lastly, routing the connection from original clock source to each newly inserted clock buffers with zero skew. A few Perl scripts and a new Visual Basic based routing tool have been developed to support the methodology implementation. The routing algorithm used in this tool is based on the exact zero skew routing algorithm. The methodology has been tested using a real design database and resulting in a significant improvement in the through put time required to complete the clock tree generation. This improvement is attributed to the ability to generate clock tree on much smaller portions of clock nets that supports of speeding up the clock tree generation process in IC design.en_US
dc.description.peerreviewedYesen_US
dc.description.publicationstatusYesen_US
dc.format.extent123535 bytes
dc.format.mimetypeapplication/pdf
dc.languageEnglishen_US
dc.language.isoen_US
dc.publisherIEEEen_US
dc.publisher.placeUnisted STatesen_US
dc.relation.ispartofstudentpublicationNen_US
dc.relation.ispartofconferencenameCanadian Conference on Electrical and Computer Engineering, 2008 (CCECE 2008)en_US
dc.relation.ispartofconferencetitleCanadian Conference on Electrical and Computer Engineering, 2008 (CCECE 2008)en_US
dc.relation.ispartofdatefrom2008-05-04en_US
dc.relation.ispartofdateto2008-05-07en_US
dc.relation.ispartoflocationNiagara Falls, Ontarioen_US
dc.rights.retentionYen_US
dc.subject.fieldofresearchElectrical and Electronic Engineering not elsewhere classifieden_US
dc.subject.fieldofresearchcode090699en_US
dc.titleZero skew clock routing for fast clock tree generationen_US
dc.typeConference outputen_US
dc.type.descriptionE1 - Conference Publications (HERDC)en_US
dc.type.codeE - Conference Publicationsen_US
gro.rights.copyrightCopyright 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.en_US
gro.date.issued2008
gro.hasfulltextFull Text


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    Contains papers delivered by Griffith authors at national and international conferences.

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