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dc.contributor.advisorMohd-Yasin, Faisal
dc.contributor.authorJadli, Utkarsh
dc.date.accessioned2021-11-02T03:56:40Z
dc.date.available2021-11-02T03:56:40Z
dc.date.issued2021-10-28
dc.identifier.doi10.25904/1912/4367
dc.identifier.urihttp://hdl.handle.net/10072/409657
dc.description.abstractPower electronic circuits are often called switching converters because of the use of power semiconductor devices that act as switches to facilitate necessary conversions of electrical energy from one form to another. There are energy losses during this conversion, and the power semiconductor devices are a major contributor to the reduced conversion efficiency. In the case of power transistors, the resistance of the device (commonly referred as “on resistance”) operating as a switch in “on” mode is responsible for the so-called conduction losses, whereas intrinsic parasitic capacitances are responsible for the energy loss during switching between “on” and “off” modes. With the increasing need to reduce the size of switching converters for applications such as battery-operated vehicles, the share of switching losses is increasing due to the use of higher voltages and increased switching frequency. In response to the need for better understanding of the switching losses, this thesis studies the nature and impact of parasitic capacitances on the efficiency of power electronic systems. The devices-under-test are commercial devices of different types i.e. power MOSFET, SJ MOSFET, SiC MOSFETs, and GaN-HEMT. The thesis is presented in the format of a “thesis by a series of published and unpublished papers” and includes six journal articles/manuscripts as individual chapters. There are four facets of the contributions made by this thesis. The first is a new measurement method for accurate quantification of power losses during turn-on and turn-off intervals. The second is two new equations for accurate calculations of both the energy storage in and a current flow through a voltage-dependent capacitor. The third facet is in terms of providing circuit designers with a simple and transparent SPICE model for GaN˗HEMTs. Finally, a new optimization method is proposed to enable circuit designers to select the best power transistors for specific power electronic systems using two parameters that are readily available in manufacturers’ datasheets. The contributions from this thesis could help the power-electronic engineers to improve the efficiency of their next-generation systems. This is becoming urgent with the rising concern for environmental protection and energy demand worldwide.en_US
dc.languageEnglish
dc.language.isoen
dc.publisherGriffith University
dc.publisher.placeBrisbane
dc.subject.keywordsparasitic capacitancesen_US
dc.subject.keywordspower lossesen_US
dc.subject.keywordsenergy storageen_US
dc.subject.keywordsenvironmental protectionen_US
dc.subject.keywordsPower Transistorsen_US
dc.subject.keywordsPower Electronic Systemen_US
dc.titleParasitic Capacitances of Power Transistors and Their Effects in Power Electronic Systemsen_US
dc.typeGriffith thesisen_US
gro.facultyScience, Environment, Engineering and Technologyen_US
gro.rights.copyrightThe author owns the copyright in this thesis, unless stated otherwise.
gro.hasfulltextFull Text
dc.contributor.otheradvisorDimitrijev, Sima
dc.contributor.otheradvisorAmini Moghadam, Hamid
gro.identifier.gurtID000000026583en_US
gro.thesis.degreelevelThesis (PhD Doctorate)en_US
gro.thesis.degreeprogramDoctor of Philosophy (PhD)en_US
gro.departmentSchool of Eng & Built Enven_US
gro.griffith.authorJadli, Utkarsh


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