A 5Gbit/s CMOS Clock and Data Recovery Circuit
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This paper presents a half-rate 5Gb/s clock and data recovery circuit. Retiming of data is done by the linear PD that provides practically no systematic offset for the frequency band of interest. The circuit was designed in a 0.18-孠CMOS process and occupies an active area of 0.2 x 0.32 mm2. The CDR exhibits an RMS jitter of ᱮ2 ps and a peak-to-peak jitter of 5ps. The power dissipation is 97mW from a 1.8-V supply
2005 IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC 2005)
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Electrical and Electronic Engineering not elsewhere classified