A 5Gbit/s CMOS Clock and Data Recovery Circuit

Thumbnail
View/Open
Author(s)
Kok-Siang, Tan
Sulaiman, Mohd Shahiman
Soon-Hwei, Tan
Reaz, Mamun BI
Mohd-Yasin, F
Griffith University Author(s)
Year published
2005
Metadata
Show full item record
Abstract
This paper presents a half-rate 5Gb/s clock and data recovery circuit. Retiming of data is done by the linear PD that provides practically no systematic offset for the frequency band of interest. The circuit was designed in a 0.18-孠CMOS process and occupies an active area of 0.2 x 0.32 mm2. The CDR exhibits an RMS jitter of ᱮ2 ps and a peak-to-peak jitter of 5ps. The power dissipation is 97mW from a 1.8-V supply
Conference Title
2005 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS
DOI
Copyright Statement
© 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Subject
Electrical and Electronic Engineering not elsewhere classified
Publication URI
Collection