Multiplier truncation in FPGA based CWT
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This paper addresses the requirement of multiplier truncation on the FPGA based continuous wavelet transform (CWT) scalogram and compares it with the one produced by Matlab-software as a reference. A method was developed to give an appropriate truncation in the multiplier stage of the CWT. The Fast Fourier Transform (FFT) algorithm was used to compute the CWT at each time and scale. The VHDL language was used for design and implementation using Altium designer software targeting Spartan 3AN FPGA. The obtained results showed that hardware implementation achieved high degree of accuracy. The produced hardware scalogram in comparing with the software one has a NMSE of 0.0013, NAD of 0.0227 and SC quality measure of 0.998.
Proceedings of the 12th International Symposium on Communications and Information Technologies