Gate capacitances of high electron mobility transistors
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The gate-drain capacitance and the sourcedrain capacitance of High Electron Mobility transistors have been measured on a computer-aided measurement system. The variation of these capacitances with transistor bias voltages is explained and compared with the trend predicted by a capacitance model used in literature. Differences in measured and calculated results arise from the assumptions used in the model. A modification to include the influence of channel potential profile is proposed.
Proceedings of ICECE2002
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HISTORY AND ARCHAEOLOGY