Gate capacitances of high electron mobility transistors
Abstract
The gate-drain capacitance and the sourcedrain capacitance of High Electron Mobility transistors have been measured on a computer-aided measurement system. The variation of these capacitances with transistor bias voltages is explained and compared with the trend predicted by a capacitance model used in literature. Differences in measured and calculated results arise from the assumptions used in the model. A modification to include the influence of channel potential profile is proposed.
Conference Title
Proceedings of ICECE2002
Copyright Statement
© 2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Subject
History and Archaeology