Show simple item record

dc.contributor.convenorJohn M.Bell & Vijay K.Varadan
dc.contributor.authorAhmadi, A
dc.contributor.authorRowlands, DD
dc.contributor.authorAlam, K
dc.contributor.editorHarlz, AJ
dc.date.accessioned2017-05-03T14:14:24Z
dc.date.available2017-05-03T14:14:24Z
dc.date.issued2006
dc.date.modified2007-03-12T08:21:50Z
dc.identifier.isbn0-8194-6066-4
dc.identifier.issn0277-786X
dc.identifier.urihttp://hdl.handle.net/10072/9717
dc.description.abstractVertical MOSFETs are gaining importance for VLSI circuit integration and for reducing the feature size. They are continuously scaled down in channel length due to the increasing need for higher packing density and higher device speed. Also 3D compaction of circuits is possible using these transistors. In order to achieve as dense and fast as possible circuits several vertical MOSFETs using different technologies have been fabricated. In this paper, 120nm vertical n-channel MOSFET uniformly doped in silicon substrate and channel region is simulated using the ISE_TCAD software, developed by the Integrated Systems Engineering and compared with one of similar fabricated transistors from the literature [4]. The results show more than 92% match between the simulated and the practical devices in terms of terminal characteristics considering the fact that the ideal mobility models as well as the most suitable mesh condition are applied to the simulation flow. Tending to scale down the length of the vertical MOSFETs and observe the short channel effects, transistors with 80nm and 100nm channel length were also simulated. As expected, shrinking the channel length results in increasing the current and decreasing the threshold voltage as part of short channel effects. Other effects such as hot-carrier and substrate current for the three devices were investigated under the certain values of gate and source voltages. Keywords: Vertical MOSFET, hot-carrier effect, short channel, mobility model, mesh
dc.description.publicationstatusYes
dc.languageEnglish
dc.language.isoeng
dc.publisherInternational Society for Optical Engineering (SPIE)
dc.publisher.placeBellingham WA 98227-0010 USA
dc.relation.ispartofstudentpublicationY
dc.relation.ispartofconferencenameConference on Microelectronics - Design, Technology and Packaging II
dc.relation.ispartofconferencetitleMICROELECTRONICS: DESIGN, TECHNOLOGY, AND PACKAGING II
dc.relation.ispartofdatefrom2005-12-12
dc.relation.ispartofdateto2005-12-14
dc.relation.ispartoflocationBrisbane, AUSTRALIA
dc.relation.ispartofpagefrom10 pages
dc.relation.ispartofpageto10 pages
dc.relation.ispartofvolume6035
dc.rights.retentionY
dc.subject.fieldofresearchcode290903
dc.titleScaling effects on deep-submicron vertical MOSFETs
dc.typeConference output
dc.type.descriptionE3 - Conferences (Extract Paper)
dc.type.codeE - Conference Publications
gro.facultyGriffith Sciences, Griffith School of Engineering
gro.date.issued2005
gro.hasfulltextNo Full Text
gro.griffith.authorRowlands, David D.


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following Collection(s)

  • Conference outputs
    Contains papers delivered by Griffith authors at national and international conferences.

Show simple item record