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dc.contributor.convenorJohn M.Bell & Vijay K.Varadanen_AU
dc.contributor.authorAhmadi, Aminen_US
dc.contributor.authorRowlands, Daviden_US
dc.contributor.authorAlam, K.en_US
dc.description.abstractVertical MOSFETs are gaining importance for VLSI circuit integration and for reducing the feature size. They are continuously scaled down in channel length due to the increasing need for higher packing density and higher device speed. Also 3D compaction of circuits is possible using these transistors. In order to achieve as dense and fast as possible circuits several vertical MOSFETs using different technologies have been fabricated. In this paper, 120nm vertical n-channel MOSFET uniformly doped in silicon substrate and channel region is simulated using the ISE_TCAD software, developed by the Integrated Systems Engineering and compared with one of similar fabricated transistors from the literature [4]. The results show more than 92% match between the simulated and the practical devices in terms of terminal characteristics considering the fact that the ideal mobility models as well as the most suitable mesh condition are applied to the simulation flow. Tending to scale down the length of the vertical MOSFETs and observe the short channel effects, transistors with 80nm and 100nm channel length were also simulated. As expected, shrinking the channel length results in increasing the current and decreasing the threshold voltage as part of short channel effects. Other effects such as hot-carrier and substrate current for the three devices were investigated under the certain values of gate and source voltages. Keywords: Vertical MOSFET, hot-carrier effect, short channel, mobility model, meshen_US
dc.publisherInternational Society for Optical Engineering (SPIE)en_US
dc.publisher.placeBellingham WA 98227-0010 USAen_US
dc.relation.ispartofconferencenameMicroelectronics, MEMS, and Nanotechnologyen_US
dc.relation.ispartofconferencetitleMicroelectronics, MEMS, and Nanotechnology SPIE volume 6035: MICROELECTRONICS: DESIGN, TECHNOLOGY, AND PACKAGING IIen_US
dc.relation.ispartoflocationQueensland University of Technologyen_US
dc.titleScaling effects on deep-submicron vertical MOSFETsen_US
dc.typeConference outputen_US
dc.type.descriptionE3 - Conference Publications (Extract Paper)en_US
dc.type.codeE - Conference Publicationsen_US
gro.facultyGriffith Sciences, Griffith School of Engineeringen_US
gro.hasfulltextNo Full Text

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    Contains papers delivered by Griffith authors at national and international conferences.

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