In this paper, we present the hardware realization of an automatic train controller modeled for KL Sentral train station. The prototype chip was developed and tested on Altera FLEX10K FPGA device and the algorithm has been specially designed to allow efficient hardware implementation. In the algorithm the automated control system employs a linear model to run the system taking into consideration inputs such as the trains actual states, desired states and error factors. The system in which connected to the individual train controller decides the optimized solution for all the active trains by feeding the information to the traffic lights throughout the station and providing the arrival time prediction to the train passengers in the station. Furthermore the algorithm takes into consideration other unpredictable factors such as faulty tracks and the delay caused by passengers. The input of the state machine are the sensors placed at various location on the tracks, while the output are the switches that control the tracks. The algorithm is rigorously simulated for all conditions. The timing analysis for the validation, functionality and performance of the model is performed using Aldec Active HDL and the logic synthesis was performed using Synplify. The models have been tested successfully, verified, and met the desired results.