EMC Modelling and Optimization for Reducing Capacitances of Interconnections with Arbitrary Shape in Multilayer VLSI Circuits

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Author(s)
Zhu, Boyuan
Lu, Junwei
Zhu, M.
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Norio Takahashi

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2011
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310580 bytes

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Sydney, Australia

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Abstract

This paper presents an EMC modelling method for the purpose of calculating the interconnect capacitance between VLSI interconnects based on the finite element method (FEM). Two- and three-dimensional interconnect models are simulated and the results of capacitance extraction are compared with experimental measurements, which proved the consistency and accuracy of FEM. Furthermore, optimizations of coupling capacitance are applied on two- and three-dimensional multilayer interconnection structures by the non-dominated sorting genetic algorithm II (NSGA-II), which shows a capacity for optimization. They are applicable to arbitrary structures in very-large-scale-integration (VLSI).

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Proceedings of COMPUMAG2011

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© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

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Microelectronics and Integrated Circuits

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