Derivation of a nonlinear variance equation and its application to SOI Technology
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Dimitrijev, S
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Abstract
An analytic nonlinear equation for variance was derived along with a method based on response surface mapping techniques to calculate the variance using the proposed equation. The technique was applied to the threshold voltage of a 0.1-孠silicon-on-insulator MOS device, and the variance value obtained was verified using Monte Carlo simulation. The threshold voltage dependence upon active-layer thickness was found to be highly nonlinear due to the device's going from the fully depleted to the partially depleted regime. Analysis of the variance showed that the effect of the nonlinear terms (18.7%) is more important than the effect of the mixed term (-0.7%) and almost as important as the contribution of the second most dominant input-process parameter (23.6%). This illustrates the importance of the proposed nonlinear equation
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IEEE Transactions on Semiconductor Manufacturing
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13
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© 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
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Manufacturing engineering
History, heritage and archaeology
Electronics, sensors and digital hardware